57.Solid State Circuits by John G. Webster (Editor) PDF

By John G. Webster (Editor)

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Since the bit lines are typically precharged high, the CMOS transmission-gate n-FET is not required. Note that the sense_L inputs are one-low predecoded signals in this case. This technique can be readily modified to have an n-FET current source and/or distributed data lines as in the circuit in Fig. 13(b). Current Sense Amps. An alternative to the familiar voltagebased differential-pair sense amp is a fully-differential current sense amp, such as the one shown in Fig. 14 (20).

W. Y. Wei and C. D. Thompson, Area-time optimal adder design, IEEE Trans. , 39 (5): 1990. 5. R. P. Brent and H. T. Kung, A regular layout for parallel adders, IEEE Trans. , 31 (3): 1982. 6. B. W. Y. -F. Chen, QAC: A CMOS implementation of the 32-bit Q adder, Proc. IEEE Int. Conf. Comput. , Port Chester, NY, October 1985. 7. T. F. Ngai, M. J. Irwin, and S. Rawat, Regular, area-time efficient carry-lookahead adders, J. Parallel Distrib. , 3: 92–105, 1986. BiCMOS MEMORY CIRCUITS 8. J. B. Kuo, H. J.

Also, the SRAM should be reset once the output data have been latched, a technique termed ‘‘post- discharge’’ in CMOS parlance. After the predecode outputs are disabled, the active word line falls and the bit-line voltages are restored or ‘‘equilibrated’’. Finally, the sense amp is equilibrated if necessary. By resetting the SRAM, access-time critical-path signals travel in only one direction, which eliminates Miller capacitance effects. Furthermore, the designer can often speed up the critical path by tuning the gates to travel faster in one direction.

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57.Solid State Circuits by John G. Webster (Editor)

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