New PDF release: Advanced Nanoscale ULSI Interconnects: Fundamentals and

By Y. Shacham-Diamand (auth.), Yosi Shacham-Diamand, Tetsuya Osaka, Madhav Datta, Takayuki Ohba (eds.)

ISBN-10: 0387958673

ISBN-13: 9780387958675

ISBN-10: 0387958681

ISBN-13: 9780387958682

Advanced Nanoscale ULSI Interconnects: primary and Applications brings a finished description of copper dependent interconnect expertise for extremely huge Scale Integration (ULSI) know-how to built-in Circuit (ICs) program. This publication experiences the fundamental applied sciences used this day for the copper metallization of ULSI functions: deposition and planarization. It describes the fabrics used, their houses, and how they're all built-in, particularly in regard to the copper integration strategies and electrochemical approaches within the nanoscale regime. The ebook additionally offers a number of novel nanoscale applied sciences that would hyperlink smooth nanoscale electronics to destiny nanoscale dependent platforms. This different, multidisciplinary quantity will entice method engineers within the microelectronics undefined; universities with courses in ULSI layout, microelectronics, MEMS and nanoelectronics; and pros within the electrochemical operating with fabrics, plating and power proprietors.

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Extra resources for Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications

Sample text

First, the SiO2 gate insulator is grown by thermal oxidation of a clean silicon wafer in a controlled atmosphere. Subsequently, a blanket layer of polysilicon is deposited by chemical vapor deposition (CVD), after which the gate fingers are defined by lithography and patterned by dry etching. In order to achieve the right threshold voltage for the transistor, the polygate on the NMOS is n-doped whereas on PMOS it is p-doped. Doping is performed by ion implantation followed by annealing of the implantation damage.

Solid-State Circuits 32, 1210 (1997) 14. Likharev, K. : Electronics below 10 nm. In: Nano and Giga, Challenges in Microelectronics. Amsterdam: Elsevier, 27 (2003) 15. Nowak, E. ; Joshi, R. : Turning silicon on its edge [double gate CMOS/FinFET technology]. IEEE Circuits and Devices Magazine 20, 20 (2004) 16. IMEC results (2005). 17. Nowak E. ; Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J. Res. & Dev. 1 Introduction Integrated electronic systems have advanced in complexity at an exponential rate during the last four decades, as measured by the number of transistors on a single silicon chip [1, 2].

MOS Device and Interconnects Scaling Physics Fig. 1 It is clear that, for state-of-the-art technologies, the gate delay is no longer the limiting factor for the circuit speed, and therefore the transistor switching speed can be traded for optimal overall performance against other device parameters such as the power dissipation. This is a very important consideration, since power, rather than speed, is becoming the main limiting factor for further miniaturization. As the technology proceeds into the nanometer era, the shift from device limited to interconnect limited design rules becomes a major trend, which is discussed at length in other chapters of this book.

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Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications by Y. Shacham-Diamand (auth.), Yosi Shacham-Diamand, Tetsuya Osaka, Madhav Datta, Takayuki Ohba (eds.)

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