By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced attempt tools for SRAMs: potent suggestions for Dynamic Fault Detection in Nanoscaled Technologies
Modern electronics relies on nanoscaled applied sciences that current new demanding situations by way of checking out and analysis. thoughts are quite vulnerable to defects due to the fact they take advantage of the know-how limits to get the top density. This booklet is a useful consultant to the checking out and prognosis of the newest iteration of SRAM, the most known kind of thoughts. Classical tools for checking out reminiscence are designed to address the so-called "static faults", yet those try out strategies aren't adequate for faults which are rising within the newest Very Deep Sub-Micron (VDSM) applied sciences. those new faults, known as "dynamic faults", should not lined via classical algorithms and require the devoted try and analysis recommendations awarded during this book.
- First e-book to offer whole, cutting-edge assurance of dynamic fault checking out for SRAM memories;
- Presents content material utilizing a "bottom-up" method, from the research of reasons of malfunctions as much as the iteration of clever try recommendations;
- Includes case reports overlaying all reminiscence parts (core-cells, tackle decoders, write drivers, experience amplifiers, etc.);
- Proposes an exhaustive research of resistive-open defects in every one reminiscence part and the ensuing dynamic fault modeling.
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Additional info for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
The conclusion is that the complexity of the memory fault simulation is equal to O(N3 ). This analysis seems to limit the feasibility of the memory fault simulation to a very small memory. 6 Conclusion 19 March test. Indeed, the fault coverage of a March test will be the same for a 1 KIbytes memory than for a 16 Mbytes memory. Moreover, if only single- and two-cell faults are considered during fault simulation, only a two-bit memory is sufficient to compute the fault coverage. Thus, the fault-simulation time is drastically reduced.
A w0 operation immediately followed by M r0 operations causes the swap of the core-cell, and a logic ‘1’ is observed at the memory output. M is the number of read operations performed after the write operation (M ≥ 1). The second group of FPs corresponds to the symmetric defect and uses essentially w1 and r1 operations: – FP3: <1w1 r1 M /0/0> A logic ‘1’ is initially stored in the cell. A w1 operation immediately followed by M r1 operations causes the swap of the core-cell content, and a logic ‘0’ is observed at the memory output.
Defect Df3: This defect produces effects similar to those of defect Df2. For the faults RDF and DRDF, induced by defects Df2 and Df3, the sensitization pattern is 0w1r1 that does not need to be applied at-speed (Borri et al. 2005). This constraint is useful for the choice of the fault detection strategy. Defect Df3 is in the refreshment loop and may lead to a dynamic Read Destructive Fault (dRDF). Defect Df4: This defect is placed in the pull-up of INV1 and may induce static and dynamic faults (Zarrineh et al.
Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies by Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel