Get Analog IC Reliability in Nanometer CMOS PDF

By Elie Maricau

ISBN-10: 1461461626

ISBN-13: 9781461461623

ISBN-10: 1461461634

ISBN-13: 9781461461630

This e-book specializes in modeling, simulation and research of analog circuit getting older. First, all very important nanometer CMOS actual results leading to circuit unreliability are reviewed. Then, transistor getting older compact types for circuit simulation are mentioned and several other equipment for effective circuit reliability simulation are defined and in comparison. eventually, the impression of transistor getting older on analog circuits is studied. Aging-resilient and aging-immune circuits are pointed out and the impression of expertise scaling is mentioned.

The types and simulation strategies defined within the booklet are meant as an relief for equipment engineers, circuit designers and the EDA group to appreciate and to mitigate the effect of getting older results on nanometer CMOS ICs.

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A DC Model The model is developed based on the reaction-diffusion (RD) approach proposed by Kufluoglu and Ashraful Alam (2004) and is also based on the LEM. As will be discussed in Sect. 2, the RD model has a number of drawbacks and is therefore not well suited to develop a BTI compact model. One of these drawbacks is the absence of support for oxide trapping in the RD model. Oxide trapping, however, is related to the typical BTI recovery effect upon stress removal. Nevertheless, the RD model can still be used to model the hot carrier effect since traps are only generated near the drain end of the transistor and therefore recovery effect is negligible.

1985). Later, when supply voltages were scaled down and graded drain junctions were introduced, HCI became a less dominant reliability problem. e. >90 nm) (Moens et al. 2010). g. inductor-based oscillators or power amplifiers) (Chouard et al. 2010; Sagong et al. 2011). Therefore, it is still important to correctly estimate the impact of HCI on the behavior of a circuit. This requires an accurate HCI compact model. HCI mainly occurs in nMOS transistors and causes a shift of important transistor parameters such as the threshold voltage and the carrier mobility.

Under the influence of the field generated by the substrate’s bulk bias, the first carriers are accelerated and potentially generate secondary carriers. These secondary carriers also accelerate in the bulk bias field towards the surface region where they further gain kinetic energy to overcome the surface energy barrier (see Fig. 6d). SGHE is observed as a rather small effect with limited contribution to the transistor degradation. As explained above, each of the four hot carrier mechanisms occurs at different transistor operating conditions.

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Analog IC Reliability in Nanometer CMOS by Elie Maricau

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