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Additional info for APIC Text of Infection Control & Epidemiology, 2nd Edition
In this section we look at how addresses get translated. The case where data is resident on disk rather than in physical memory is covered in Chapter 6. PA-RISC processors operate in one of two modes: narrow or wide. 1 processors are always narrow, and they operate on 32-bit addresses. 0 processors can be narrow or wide at any time depending on the setting of the W-bit in the PSW. Because the addresses are handled differently in these two cases, we look at both possibilities. We also look at the memory layout for both kernel mode and user mode.
For example, HP-UX refers to a "Protection Fault" when this is strictly a trap, not a fault. However, all four types of interruptions are handled in the same way, so it's really just a matter of terminology. Also note that the terms interrupt and interruption are sometimes confused. Strictly speaking, an event (other than a BRANCH) that causes the flow of control to change is an interruption. One particular type of interruption is an interrupt, which is a signal from an external device. Each possible type of interruption is given a predetermined priority within the system, and the various types are organized into interruption groups.
The load instruction might then be LDW 8(r3), r4 The displacement portion of the instruction is the offset from the beginning of the structure, which is known at compile time. The base register holds the pointer to the beginning of the structure, which is not known until runtime. Base Register Modification Another variation of the STORE and LOAD instructions provides base register modification. That is, in addition to moving data to or from memory, the instruction also modifies the specified base register.
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